The present invention generally relates to fabrication methods and resulting structures for semiconductor devices. More specifically, the present invention relates to methods and structure for controlling the amount and type of grain boundaries in high aspect-ratio conductive regions of a metallization network.
Semiconductor devices and components, which are referred to collectively herein as integrated circuit (IC) components, include a plurality of circuit elements (e.g., transistors, resistors, diodes, capacitors, etc.) communicatively connected together on a semiconductor substrate (i.e., a wafer or a chip). IC components are coupled to one another by a metallization network of interconnected layers and conductive regions formed in regions in the wafer/chip. The interconnect layers and conductive regions are often formed from copper (Cu), which facilitates the development of smaller metal components, reduces energy usage, and facilitates the fabrication of higher-performance processors. Copper, like most metals, is commonly found in polycrystalline form.